A serial bit stream may be transmitted with biphase mark encoding to minimize the DC component within the stream and to enable clock recovery therefrom. As will be understood by those skilled in the art, biphase mark encoding is employed by the International Engineering Consortium (IEC) 60958 standard, the AES3 digital audio standard and the Sony/Philips Digital Interconnect Format (SPDIF) standard, which is typically used for transporting stereo digital audio signals on PC audio cards, CD players, DVD players, car audio systems and other systems that transmit or receive stereo digital audio, for example.
As illustrated by FIG. 1, after biphase mark encoding, logic 1 data values are transmitted with center transitions, but logic 0 data values are not. Biphase mark bit streams also switch polarity at each data bit boundary. Accordingly, because the value of each data bit is determined by whether there is a transition at the center of a bit or not, the actual polarity of the bit stream signal is irrelevant. There are only three valid symbols in a biphase mark bit stream: 1UI, 2UI and 3UI, where “UI” denotes “unit interval.” As illustrated by FIG. 2, a biphase encoding block consists of 192 frames, with each frame including two sub-frames. Every sub-frame consists of a preamble part and a channel data part. Each preamble part contains two biphase mark encoding violations, as illustrated by TABLE 1. There are three types of preambles: X, Y and Z. Sub-frame 2 always begins with a Y preamble and sub-frame 1 almost always begins with an X preamble, with an exception that every 192 frames, the X preamble in sub-frame 1 is replaced with a Z preamble, which indicates a block start (i.e., start of Frame 0).
TABLE 1PRECEDING STATEBI-PHASE PATTERNSPREAMBLE01CHANNELX1110001000011101CHANNEL 1Y1110010000011011CHANNEL 2Z1110100000010111CHANNEL 1 &BLOCK START
As illustrated by FIG. 3, a conventional clock recovery circuit 10 may utilize a phase-locked loop (PLL) integrated circuit (digital or analog) to generate a recovered biphase clock that tracks to a biphase mark encoded data stream and to use this recovered clock to decode the encoded data stream into the original source data. An additional clock recovery circuit that utilizes a PLL integrated circuit is disclosed in U.S. Pat. No. 7,136,446 to Schmidt, entitled “Method and Apparatus for Data and Clock Recovery in a Biphase-Coded Data Signal.” Techniques to recover clock signals from biphase mark bit streams are also disclosed in U.S. Pat. No. 7,310,390 to Bertram, entitled “Decoding Coded Data Streams,” U.S. Pat. No. 6,768,433 to Toth et al., entitled “Method and System for Decoding Biphase-Mark Encoded Data,” and US 2007/0047638 to Lam et al., entitled “System and Method for Decoding an Audio Signal.”